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CapSense Applications
CY8C20X36A/46A/66A/96A (R)
Features

1.71V to 5.5V Operating Range Low Power CapSenseTM Block Configurable Capacitive Sensing Elements Supports Combination of CapSense Buttons, Sliders, Touchpads, Touch Screens, and Proximity Sensor Powerful Harvard Architecture Processor M8C Processor Speeds Running to 24 MHz Low Power at High Speed Interrupt Controller Temperature Range: -40C to +85C Flexible On-Chip Memory Three Program/Data Storage Size Options: * CY8C20X36A: 8K Flash / 1K SRAM * CY8C20x46A, CY8C20x96A: 16K Flash / 2K SRAM * CY8C20x66A: 32K Flash / 2K SRAM 50,000 Flash Erase/Write Cycles Partial Flash Updates Flexible Protection Modes In-System Serial Programming (ISSP) Full Speed USB Available on CY8C20646A, CY8C20666A, CY8C20x96A only 12 Mbps USB 2.0 Compliant Eight Unidirectional Endpoints One Bidirectional Control Endpoint Dedicated 512 Byte Buffer Internally Regulated at 3.3V Precision, Programmable Clocking Internal Main Oscillator: 6/12/24 MHz 5% Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep Timers Precision 32 kHz Oscillator for Optional External Crystal 0.25% Accuracy for USB with No External Components (CY8C20646A, CY8C20666A, CY8C20x96A only) Programmable Pin Configurations Up to 36 GPIO (Depending on Package) Dual Mode GPIO: All GPIO Support Digital I/O and Analog Input 25 mA Sink Current on All GPIO Pull up, High Z, Open Drain Modes on All GPIO CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1: * 20 mA (at 3.0V) Total Source Current on Port 0 * 20 mA (at 3.0V) Total Source Current on Port 1 Selectable, Regulated Digital I/O on Port 1 Configurable Input Threshold on Port 1 Hot Swap Capability on all Port 1 GPIO
Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of I/O High PSRR Comparator Low Dropout Voltage Regulator for All Analog Resources Additional System Resources I2C Slave: * Selectable to 50 kHz, 100 kHz, or 400 kHz * No Clock Stretching Required (under most conditions) * Implementation During Sleep Modes with Less Than 100 A * Hardware Address Validation SPITM Master and Slave: Configurable 46.9 kHz to 12 MHz Three 16-Bit Timers Watchdog and Sleep Timers Internal Voltage Reference Integrated Supervisory Circuit 8-bit Delta-Sigma Analog-to-Digital Converter Two General Purpose High Speed, Low Power Analog Comparators Complete Development Tools Free Development Tool (PSoC DesignerTM) Full Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Package Options CY8C20X36A: * 16-Pin 3 x 3 x 0.6 mm QFN * 24-Pin 4 x 4 x 0.6 mm QFN * 32-Pin 5 x 5 x 0.6 mm QFN * 48-Pin SSOP * 48-Pin 7 x 7 x 1.0 mm QFN CY8C20x46A: * 16-Pin 3 x 3 x 0.6 mm QFN * 24-Pin 4 x 4 x 0.6 mm QFN * 32-Pin 5 x 5 x 0.6 mm QFN * 48-Pin SSOP * 48-Pin 7 x 7 x 1.0 mm QFN (with USB) CY8C20x96A: * 24-Pin 4 x 4 x 0.6 mm QFN (with USB) * 32-Pin 5 x 5 x 0.6 mm QFN (with USB) CY8C20x66A: * 32-Pin 5 x 5 x 0.6 mm QFN * 48-Pin 7 x 7 x 1.0 mm QFN (with USB) * 48-Pin SSOP

Cypress Semiconductor Corporation Document Number: 001-54459 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 14, 2009
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Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V LDO
PWRSYS (Regulator)
PSoC CORE
SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Interrupt Controller 8K/16K/32K Flash Nonvolatile Memory Sleep and Watchdog
Supervisory ROM (SROM)
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator (IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE SYSTEM
CapSense Module Two Comparators
Analog Reference
Analog Mux
SYSTEM BUS
USB
I2C Slave
Internal Voltage References
System Resets
POR and LVD
SPI Master/ Slave
Three 16-Bit Programmable Timers
Digital Clocks
SYSTEM RESOURCES
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PSoC(R) Functional Overview
The PSoC family consists of on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logic Block Diagram on page 2, is comprised of three main areas: the Core, the CapSense Analog System, and the System Resources (including a full speed USB port). A common, versatile bus allows connection between I/O and the analog system. Each CY8C20X36A/46A/66A/96A PSoC Device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 36 general purpose IO (GPIO) are also included. The GPIO provides access to the MCU and analog mux.
Figure 1. Analog System Block Diagram
IDAC
Analog Global Bus
Vr Reference Buffer
Cinternal
Comparator
Mux Mux
Refs
PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as configurable USB and I2C slave/SPI master-slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. The Analog System is composed of the CapSense PSoC block and an internal 1.2V analog reference, which together support capacitive sensing of up to 36 inputs.
CapSenseCounters
CSCLK IMO CapSense Clock Select Oscillator
Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:

CapSense Analog System
The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports.
Complex capacitive sensing interfaces, such as sliders and touchpads. Chip-wide mux that allows analog input from any I/O pin. Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, which can be found under http://www.cypress.com > Documentation > Application Notes. In general, and unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) for CapSense applications is 5:1.
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Additional System Resources
System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here:
Getting Started
The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PSoC(R) Programmable System-on-ChipTM Technical Reference Manual for CY8C20X36A/46A/66A/96A PSoC Devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc.
The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). The I2C hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power-On-Reset) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. A register-controlled bypass mode allows the user to disable the LDO. Standard Cypress PSoC IDE tools are available for debugging the CY8C20X36A/46A/66A/96A family of parts. However, the additional trace length and a minimal ground plane in the FlexPod can create noise problems that make it difficult to debug the design. A custom bonded On-Chip Debug (OCD) device is available in an 48-pin QFN package. The OCD device is recommended for debugging designs that have high current and/or high analog accuracy requirements. The QFN package is compact and is connected to the ICE through a high density connector.
Application Notes
Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab.

Development Kits
PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800541-4736.
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Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows XP and Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third-party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to be merged seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
PSoC Designer Software Subsystems
System-Level View The system-level view is a drag-and-drop visual embedded system design environment based on PSoC Express. In this view you solve design problems the same way you might think about the system. Select input and output devices based upon system requirements. Add a communication interface and define the interface to the system (registers). Define when and how an output device changes state based upon any/all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC devices that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.x. You choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. You configure the user modules for your chosen application and connect them to each other and to the proper pins. Then you generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over onchip resources. All views of the project share common code editor, builder, and common debug, emulation, and programming tools.
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Designing with PSoC Designer
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify, and Debug
Organize and Connect
You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog-todigital converter (ADC) to convert the potentiometer's output to a digital signal, and a PWM to control the fan. In the chip-level view, you perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources.
Select Components
Both the system-level and chip-level views provide a library of pre-built, pre-tested hardware peripheral components. In the system-level view these components are called "drivers" and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2Cbus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view the components are called "user modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
Configure Components
Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design.
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Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document. Table 1. Acronyms Acronym AC API CPU DC FSR GPIO GUI ICE ILO IMO I/O LSb LVD MSb POR PPOR PSoC(R) SLIMO SRAM Description alternating current application programming interface central processing unit direct current full scale range general purpose I/O graphical user interface in-circuit emulator internal low speed oscillator internal main oscillator input/output least-significant bit low voltage detect most-significant bit power on reset precision power on reset Programmable System-on-ChipTM slow IMO static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 11 on page 17 lists all the abbreviations used to measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
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Pinouts
The CY8C20X36A/46A/66A/96A PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital I/O.
16-Pin QFN (No E-Pad)
Table 2. Pin Definitions - CY8C20236A, CY8C20246A PSoC Device [2] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IOH Power IOH IOH IOH I I I Type Digital I/O I/O IOHR IOHR IOHR IOHR Power IOHR IOHR IOHR Input I I I I Analog I I I I I I Name Description Figure 2. CY8C20236A, CY8C20246A PSoC Device
P0[1], AI P0[3], AI P0[7], AI Vdd 16 15 5 6 7 AI, DATA1, I2C SDA, SPI CLK, P1[0] AI, SPI CLK, P1[3] AI, CLK1, SPI MOSI, P1[1] Vss 8 AI, XOut, P2[5] AI, XIn, P2[3] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] 1 2 14 13 3 4
QFN (Top View) 11
P2[5] Crystal output (XOut) P2[3] Crystal input (XIn) P1[7] I2C SCL, SPI SS P1[5] I2C SDA, SPI MISO P1[3] SPI CLK P1[1] ISSP CLK[1], I2C SCL, SPI MOSI Vss Ground connection P1[0] ISSP DATA[1], I2C SDA, SPI CLK P1[2] P1[4] Optional external clock (EXTCLK) XRES Active high external reset with internal pull down P0[4] Vdd P0[7] P0[3] Integrating input P0[1] Integrating input Supply voltage
12
10 9
P0[4], AI XRES P1[4], EXTCLK, AI P1[2], AI
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes 1. These are the ISSP pins, which are not High Z at POR (Power On Reset). 2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
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24-Pin QFN
Table 3. Pin Definitions - CY8C20336A, CY8C20346A [2, 3]
P0[1], AI P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI
21 24 22 23 20 19
Type Pin No. Digital Analog Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP IOH IOH IOH IOH Power I/O IOH IOH IOH IOH Power I I I I Power IOHR IOHR IOHR IOHR Input I I I I I I I I I I/O I/O I/O IOHR IOHR IOHR IOHR I I I I I I I P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Vss
Description
Crystal output (XOut) Crystal input (XIn) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK[1], I2C SCL, SPI MOSI No connection Ground connection ISSP DATA[1], I2C SDA, SPI CLK Optional external clock input (EXTCLK) Active high external reset with internal pull down
Figure 3. CY8C20336A, CY8C20346A PSoC Device
AI, XOut, P2[5] AI, XIn, P2[3]
1 2 3 4 5 6
18 17 16 15 14
Supply voltage
Integrating input Integrating input Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Note 3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal.
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AI, DATA2, I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4]
AI, CLK2, I2C SCL SPI MOSI, P1[1] NC Vss
10
11 12
7
8
9
AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3]
QFN
(Top View)
13
P0[4], AI P0[2], AI P0[0], AI P2[0], AI XRES P1[6], AI
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24-Pin QFN with USB
Table 4. Pin Definitions - CY8C20396A PSoC Device [2, 3]
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP Type Digital I/O I/O I/O IOHR IOHR IOHR IOHR Power I/O I/O Power IOHR IOHR IOHR IOHR I I I I I I Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] VSS D+ DVDD P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] VSS Integrating input Integrating input Thermal pad must be connected to Ground Active high external reset with internal pull down Optional external clock input (EXTCLK) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK, I2C SCL, SPI MOSI Ground USB D+ USB DSupply ISSP DATA, I2C SDA
P2[5] P2[3]
Description
Figure 4. CY8C20396A PSoC Device
P0[1], AI P0[3] P0[5] P0[7] P0[6] P0[4]
22 23 20 24 19 21 1 18 17 16 14 11 10 12 8 9 13 2 3 4 5 7 6
P2[1] I2 C SCL, SPI SS, P1[7] I2 C SDA, SPI MISO, P1[5] SPI CLK, P1[3]
QFN
( Top View 15 )
P0[2] P0[0] XRES P1[6] P1[4] , EXTCLK P1[2]
RESET INPUT IOH IOH IOH IOH IOH IOH IOH IOH Power I I I I I I I I
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
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ISSP CLK, I2C SCL, SPI MOSI, P1[1] Vss D+ DVDD ISSP DATA, I2C SDA, P1[0]
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32-Pin QFN
Table 5. Pin Definitions - CY8C20436A, CY8C20446A, CY8C20466A PSoC Device [2, 3] Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 I/O IOHR IOHR IOHR IOHR Input I
Type Digital
IOH I/O I/O I/O I/O I/O I/O IOHR IOHR IOHR IOHR Power I I I I
Analog
I I I I I I I I I I I
Name
P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0]
Description
Integrating input Crystal output (XOut)
Figure 5. CY8C20436A, CY8C20446A, CY8C20466A
PSoC Device
Vss P0 [3 ], AI P0 [5 ], AI P0 [7 ], AI Vd d P0 [6 ], AI 28 27 P0 [4 ], AI P0 [2 ], AI 26 25
32 31
Crystal input (XIn)
I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK. ISSP CLK[1], I2C SCL, SPI MOSI. Ground connection. ISSP DATA[1], I2C SDA., SPI CLK Optional external clock input (EXTCLK) Active high external reset with internal pull down
AI, P0[1] AI, P2[7] AI, XOut, P2[5] AI, XIn, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7]
1 2 3 4 5 6 7 8
30 29
QFN
(Top View)
9
10 11 12
13 14
AI, CLK4, I2C SCL, SPI MOSI, P1[1] V ss AI, DATA1, I2C SDA, SPI CLK, P1[0] AI, P 1[2]
AI, I2C SDA , SP I MISO , P 1[5] A I, SP I CLK , P 1[3]
19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP
I/O I/O I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Power Power
I I I I I I I I I I I I
P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Integrating input Ground connection Center pad must be connected to ground Supply voltage
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-54459 Rev. **
AI, E XTCLK , P 1[4] AI, P 1[6]
15 16
24 23 22 21 20 19 18 17
P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES
Page 11 of 38
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CY8C20X36A/46A/66A/96A
32-Pin QFN (with USB)
Table 6. Pin Definitions - CY8C20496A PSoC Device [2, 3]
Vss P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI 28 27 P0[4], AI P0[2], AI 26 25
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Type Digital
IOH I/O I/O I/O IOHR IOHR IOHR IOHR Power I I Power IOHR IOHR IOHR IOHR Input I/O I I I I I
Analog
I I I I I I I I
Name
P0[1] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] VSS D+ DVdd P1[0] P1[2] P1[4] P1[6] XRES P3[0] EXTCLK XTAL Out XTAL In
Description
Figure 5. CY8C20496A PSoC Device
32 31 AI , P0[1] XTAL OUT, P2[5] XTAL IN , P2[3] AI, P2[1] I2C SCL, SPI SS, P1[7] I2C SDA, SPI MISO, P1[5] SPI CLK , P1[3] TC CLK, I2C SCL, SPI MOSI,P1[1]
30 29
I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK TC CLK, I2C SCL, SPI MOSI Ground Pin USB PHY USB PHY Power pin TC DATA*, I2C SDA, SPI CLKI
9
10 11 12
13 14
USB PHY DVdd TC, DATA1 , I2C SDA, SPI CLK, P1[0] AI, P1[2]
Active high external reset with internal pull down
19 20 21 22 23 24 25 26 27 28 29 30 31 32
I/O I/O I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Power
I I I I I I I I I I I I
P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Ground Pin Power Pin
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-54459 Rev. **
AI, E XTCLK, P1[4] AI, P1[6]
Vss USB PHY, D+
15 16
1 2 3 4 5 6 7 8
QFN
( Top View )
24 23 22 21 20 19 18 17
P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES
Page 12 of 38
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CY8C20X36A/46A/66A/96A
48-Pin SSOP
Table 7. Pin Definitions - CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device[2] Pin No. Analog Digital Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC I/O I/O I/O I/O I/O I/O I I I I I I P4[3] P4[1] NC P3[7] P3[5] P3[3] P3[1] NC NC IOHR I IOHR I IOHR I IOHR I IOHR I IOHR I IOHR I IOHR I P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] NC NC NC NC No connection No connection No connection EXT CLK No connection No connection I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK TC CLK[1], I2C SCL, SPI MOSI Ground Pin TC DATA[1], I2C SDA, SPI CLK No connection No connection No connection XTAL Out XTAL In
Description
Figure 6. CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device
AI, P0[7] AI, P0[5] AI, P0[3] AI P0[1] AI, P2[7] XTALOUT, P2[5] XTALIN, P2[3] AI, P2[1] NC NC AI, P4[3] AI, P4[1] NC AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1] NC NC I2C SCL, SPI SS, P1[7] I2C SDA, SPI MISO, P1[5] SPI CLK, P1[3] TC CLK, I2C SCL, SPI MOSI, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
IOH IOH IOH IOH I/O I/O I/O I/O
I I I I I I I I
SSOP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDD P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[6], AI P3[4], AI P3[2], AI P3[0], AI XRES NC NC NC NC NC NC P1[6], AI P1[4], EXT CLK P1[2], AI P1[0], TC DATA, I2C SDA, SPI CLK
Pin No.
Analog
Digital
No connection
Name
P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Power Pin
Description
33 34 35 36 37 38 39 40 I/O I/O I/O I/O I/O I I I I I
NC NC XRES P3[0] P3[2] P3[4] P3[6] P2[0]
No connection No connection
41 42
I/O I/O I/O
I I I
Active high external reset with internal 43 pull down 44 45 46 47 48
IOH I IOH I IOH I IOH I Power
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Document Number: 001-54459 Rev. **
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CY8C20X36A/46A/66A/96A
48-Pin QFN
Table 8. Pin Definitions - CY8C20636A PSoC Device [2, 3] Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Power IOHR IOHR IOHR IOHR Input I/O I/O I/O I I I I I I I IOHR IOHR Power I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I
Analog
Digital
Figure 7. CY8C20636A PSoC Device
Vdd P0[6], AI P0[4], AI Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC P0[1], AI P0[2], AI P0[0], AI 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] ,AI P2[2] ,AI P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[6] ,AI P3[4] , AI P3[2] ,AI P3[0 ] , AI XRES P1[6] , AI
Name
NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] Vss DNU DNU Vdd P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2]
Description
No connection Crystal output (XOut) Crystal input (XIn)
NC AI , P2[7] AI , XOut, P2[5] AI , XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI P3[1] AI, I2 C SCL, SPI SS, P1[7]
46 45 44 43
1 2 3 4 5 6
QFN
( Top View )
7 8 9 10 11 12
I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[1], I2C SCL, SPI MOSI Ground connection
Supply voltage ISSP DATA[1], I2C SDA, SPI CLK Optional external clock input (EXTCLK) Active high external reset with internal pull down
Pin No.
30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] 40 41 42 43 44 45 46 47 48 CP
Analog
Digital
P3[4]
Name
P0[6] Vdd NC NC Supply voltage No connection No connection
IOH
I
Power
IOH IOH IOH IOH
I I I I
P0[7] P0[5] P0[3] Vss P0[1] Vss Center pad must be connected to ground Integrating input Ground connection
Power Power
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-54459 Rev. **
NC NC SPI CLK, A I, P1[3] AI, CLK6 , I2C SCL, SPI MOSI, P1[1] Vss DNU DNU Vdd AI, DATA1, I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4]
I2C SDA, SPI MISO, A I, P1[5]
13 14 15 16 17 18 19 20 21 22 23 24
42 41 40 39 38 37
48 47
Description
Page 14 of 38
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CY8C20X36A/46A/66A/96A
48-Pin QFN with USB
Table 9. Pin Definitions - CY8C20646A, CY8C20666A PSoC Device [2, 3] Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 IOHR IOHR Power I/O I/O Power IOHR IOHR IOHR IOHR Input I/O I/O I/O I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I
Analog
Digital
Figure 8. CY8C20646A, CY8C20666A PSoC Device
Vdd P0[6], AI P0[4], AI Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC P0[1], AI P0[2], AI P0[0], AI 36 35 34 33 32 31 30 29 28 27 26 25 P2[6], AI P2[4],AI P2[2],AI P2[0],AI P4[2], AI P4[0],AI P3[6],AI P3[4], AI P3[2], AI P3[0 ], AI XRES P1[6], AI
Name
NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] Vss D+ DVdd P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2]
Description
No connection Crystal output (XOut) Crystal input (XIn)
NC AI , P2[7] AI, XOut, P2[5] AI, XIn , P2[3] AI , P2[1] AI, P4[3] AI, P4[1] AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] 1 2 3 4 5 6
48 47 46 45 44 43
QFN
(Top View)
I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[1], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA[1], I2C SDA, SPI CLK Optional external clock input (EXTCLK) Active high external reset with internal pull down
Pin No.
30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] 40 41 42 43 44 45 46 47 48 CP
Analog
Digital
P3[4]
Name
P0[6] Vdd NC NC Supply voltage No connection No connection
IOH
I
Power
IOH IOH IOH IOH
I I I I
P0[7] P0[5] P0[3] Vss P0[1] Vss Center pad must be connected to ground Integrating input Ground connection
Power Power
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-54459 Rev. **
NC NC SPI CLK, A I, P1[3] AI, CLK6, I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd AI, DATA1, I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4]
I2C SDA, SPI MISO, A I, P1[5]
13 14 15 16 17 18 19 20 21 22 23 24
7 8 9 10 11 12
42 41 40 39 38 37
Description
Page 15 of 38
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CY8C20X36A/46A/66A/96A
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging.[4] Table 10. Pin Definitions - CY8C20066A PSoC Device [2, 3] Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 IOHR IOHR Power I/O I/O Power IOHR IOHR I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I
Analog
Digital
Figure 9. CY8C20066A PSoC Device
OCDO Vdd P0[6], AI P0[4], AI Vss P0[3], AI P0[5 ], AI P0[7], AI OCDE
Name
OCDOE P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] P1[1] Vss D+ DVdd P1[0] P1[2]
Description
OCD mode direction pin Crystal output (XOut) Crystal input (XIn)
OCDO AE , P2[7] I AI, XOut, P2[5] AI, XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] 1 2 3 4 5 6 7 8 9 10 11 12 P0[1], AI
48 47 46 45 44 43
42 41 40 39 38 37
P0[2], AI P0[0], AI 36 35 34 33 32 31 30 29 28 27 26 25 P2[6], AI P2[4], AI P2[2], AI P2[0], AI P4[2], AI P4[0], AI P3[6], AI P3[4], AI P3[2], AI P3[0], AI XRES P1[6], AI
QFN
(Top View)
I2C SCL, SPI SS I2C SDA, SPI MISO OCD CPU clock output OCD high speed clock output SPI CLK. ISSP CLK[1], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA(1), I2C SDA, SPI CLK
Pin No.
24 25 26 27 28 29 30 31 32 33 34 35 36 IOHR IOHR Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I P1[4] P1[6] XRES P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] Active high external reset with internal pull down Optional external clock input (EXTCLK) 37 38 39 40 41 42 43 44 45 46 47 48 CP
Analog
Digital
Name
P0[0] P0[2] P0[4] P0[6] Vdd OCDO OCDE Supply voltage
IOH IOH IOH IOH Power
I I I I
IOH IOH IOH Power IOH Power
I I I I
P0[7] P0[5] P0[3] Vss P0[1] Vss Center pad must be connected to ground Integrating input Ground connection
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Note 4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
Document Number: 001-54459 Rev. **
I2C SDA, SPI MISO, AI, P1[5] CCLK HCLK SPI CLK, A I, P1[3] AI, CLK6, I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd AI, DATA1, I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4]
13 14 15 16 17 18 19 20 21 22 23 24
Description
OCD even data I/O OCD odd data output
Page 16 of 38
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CY8C20X36A/46A/66A/96A
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20X36A/46A/66A/96A PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Figure 10. Voltage versus CPU Frequency Figure 11. IMO Frequency Trim Options
5.5V
5.5V
Vdd Voltage
l id g Va ratin n pe io O Reg
Vdd Voltage
SLIMO Mode = 01
SLIMO Mode = 00
SLIMO Mode = 10
1.71V 750 kHz 3 MHz CPU Frequency 24 MHz
1.71V 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz
IMO Frequency
The following table lists the units of measure that are used in this section. Table 11. Units of Measure Symbol C dB fF Hz KB Kbit kHz ksps k MHz M A F H s W decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatts Unit of Measure degree Celsius mA ms mV nA ns nV pA pF pp ppm ps sps s V Symbol milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Unit of Measure
Document Number: 001-54459 Rev. **
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 12. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Conditions Higher storage temperatures reduces data retention time. Recommended Storage Temperature is +25C 25C. Extended duration storage temperatures above 85oC degrades reliability. Min -55 Typ +25 Max +125 Units C
Vdd VIO VIOZ IMIO ESD LU
Supply Voltage Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch up Current Human Body Model ESD In accordance with JESD78 standard
-0.5 Vss - 0.5 Vss -0.5 -25 2000 -
- - - - - -
+6.0 Vdd + 0.5 Vdd + 0.5 +50 - 200
V V V mA V mA
Operating Temperature
Table 13. Operating Temperature Symbol TA TJ Description Ambient Temperature Operational Die Temperature The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 34. The user must limit the power consumption to comply with this requirement. Conditions Min -40 Typ - Max +85 Units C
-40
-
+100
C
Document Number: 001-54459 Rev. **
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CY8C20X36A/46A/66A/96A
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14. DC Chip-Level Specifications Symbol Vdd IDD24 Description Supply Voltage Supply Current, IMO = 24 MHz Conditions Refer the table DC POR and LVD Specifications on page 24 Conditions are Vdd = 3.0V, TA = 25C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current Conditions are Vdd = 3.0V, TA = 25C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current Conditions are Vdd = 3.0V, TA = 25C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current Vdd = 3.0V, TA = 25C, I/O regulator turned off Min 1.71 - Typ - 2.88 Max 5.5 4.0 Units V mA
IDD12
Supply Current, IMO = 12 MHz
-
1.71
2.6
mA
IDD6
Supply Current, IMO = 6 MHz
-
1.16
1.8
mA
ISB0 ISB1
Deep Sleep Current
- -
0.1 1.07
- 1.5
A A
Standby Current with POR, LVD and Vdd = 3.0V, TA = 25C, I/O regulator turned Sleep Timer off
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and -40C TA 85C, 2.4V to 3.0V and -40C TA 85C, or 1.71V to 2.4V and -40C TA 85C, respectively. Typical parameters apply to 5V and 3.3V at 25C and are for design guidance only. Table 15. 3.0V to 5.5V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out High Output Voltage Port 1 Pins with LDO Regulator Enabled for 3V Out IOH < 10 A, maximum of 10 mA source current in all IOs IOH = 1 mA, maximum of 20 mA source current in all IOs IOH < 10 A, maximum of 10 mA source current in all IOs IOH = 5 mA, maximum of 20 mA source current in all IOs IOH < 10 A, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs Conditions Min 4 Vdd - 0.2 Vdd - 0.9 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V
VOH4
Vdd - 0.9
-
-
V
VOH5
2.85
3.00
3.3
V
VOH6
2.20
-
-
V
VOH7
IOH < 10 A, Vdd > 2.7V, maximum of High Output Voltage Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs Out IOH = 2 mA, Vdd > 2.7V, maximum of High Output Voltage Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs Out High Output Voltage IOH < 10 A, Vdd > 2.7V, maximum of Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs Out
2.35
2.50
2.75
V
VOH8
1.90
-
-
V
VOH9
1.60
1.80
2.1
V
Document Number: 001-54459 Rev. **
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Table 15. 3.0V to 5.5V DC GPIO Specifications (continued) Symbol VOH10 Description Conditions Min 1.20 Typ - Max - Units V High Output Voltage IOH = 1 mA, Vdd > 2.7V, maximum of Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs Out Low Output Voltage IOL = 25 mA, Vdd > 3.3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5])
VOL
-
-
0.75
V
VIL VIH VH IIL CPIN
Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Pin Capacitance Package and pin dependent Temp = 25C
- 2.00 - - 0.5
- - 80 0.001 1.7
0.80 - 1 5
V V mV A pF
Document Number: 001-54459 Rev. **
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Table 16. 2.4V to 3.0V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH < 10 A, maximum of 10 mA source current in all IOs IOH = 0.2 mA, maximum of 10 mA source current in all IOs IOH < 10 A, maximum of 10 mA source current in all IOs IOH = 2 mA, maximum of 10 mA source current in all IOs Conditions Min 4 Vdd - 0.2 Vdd - 0.4 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V
VOH4
Vdd - 0.5
-
-
V
VOH5A
IOH < 10 A, Vdd > 2.4V, maximum of High Output Voltage Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs Out High Output Voltage IOH = 1 mA, Vdd > 2.4V, maximum of Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs Out Low Output Voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5])
1.50
1.80
2.1
V
VOH6A
1.20
-
-
V
VOL
-
-
0.75
V
VIL VIH VH IIL CPIN
Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins Package and pin dependent Temp = 25oC
- 1.4 - - 0.5
- - 80 0.001 1.7
0.72 - 1 5
V V mV A pF
Table 17. 1.71V to 2.4V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull up Resistor High Output Voltage Port 2 or 3 Pins High Output Voltage Port 2 or 3 Pins High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 High Output Voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 Low Output Voltage IOH = 10 A, maximum of 10 mA source current in all I/Os IOH = 0.5 mA, maximum of 10 mA source current in all I/Os IOH = 100 A, maximum of 10 mA source current in all I/Os IOH = 2 mA, maximum of 10 mA source current in all I/Os IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) Conditions Min 4 Vdd - 0.2 Vdd - 0.5 Vdd - 0.2 Typ 5.6 - - - Max 8 - - - Units k V V V
VOH4
Vdd - 0.5
-
-
V
VOL
-
-
0.4
V
VIL VIH
Input Low Voltage Input High Voltage
- 0.65 x Vdd
- -
0.3 x Vdd
V V
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Table 17. 1.71V to 2.4V DC GPIO Specifications (continued) Symbol VH IIL CPIN Description Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins Package and pin dependent Temp = 25oC Conditions Min - - 0.5 Typ 80 0.001 1.7 Max - 1 5 Units mV A pF
Table 18.DC Characteristics - USB Interface Symbol Rusbi Rusba Vohusb Volusb Vdi Vcm Vse Cin Iio Rps2 Rext Description USB D+ Pull Up Resistance USB D+ Pull Up Resistance Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage PS/2 Pull Up Resistance External USB Series Resistor In series with each USB pin On D+ or D- line -10 3 21.78 0.2 0.8 0.8 With idle bus While receiving traffic Conditions Min 0.900 1.425 2.8 Typ 5 22.0 2.5 2.0 50 +10 7 22.22 Max 1.575 3.090 3.6 0.3 Units k k V V V V V pF A k
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. DC Analog Mux Bus Specifications Symbol RSW RGND Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to Vss Conditions Min - - Typ - - Max 800 800 Units
The maximum pin voltage for measuring RSW and RGND is 1.8V
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. DC Comparator Specifications Symbol VLPC ILPC VOSLPC Description Low Power Comparator (LPC) common mode LPC supply current LPC voltage offset Conditions Maximum voltage limited to Vdd Min 0.0 - - Typ - 10 2.5 Max 1.8 40 30 Units V A mV
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Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: -40C <= TA <= 85C, 1.71V <= Vdd <= 5.5V. Table 21. Comparator User Module Electrical Specifications Symbol TCOMP Offset Current Supply voltage >2V Supply voltage <2V Average DC current, 50 mV overdrive Power Supply Rejection Ratio Power Supply Rejection Ratio 0 Description Comparator Response Time Conditions 50 mV overdrive Min Typ 70 2.5 20 80 40 1.5 Max 100 30 80 Units ns mV A dB dB V
PSRR Input Range
ADC Electrical Specifications
Table 22. ADC User Module Electrical Specifications Symbol Input VIN CIN RES S8 Input Voltage Range Input Capacitance Resolution 8-Bit Sample Rate Settings 8, 9, or 10 Data Clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) Data Clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) For any configuration For any configuration -1 -2 0 Source is chip's internal main oscillator. See device data sheet for accuracy. 2.25 15 275 8 23.4375 This gives 72% of maximum code Vss 1.3 5 10 V pF Bits ksps Description Conditions Min Typ Max Units
S10
10-Bit Sample Rate
5.859
ksps
DC Accuracy DNL[5] INL Eoffset IADC FCLK Differential Nonlinearity Integral Nonlinearity Offset Error Operating Current Data Clock +2 +2 90 350 12 LSB LSB mV A MHz
PSRR
Power Supply Rejection Ration PSRR (Vdd>3.0V) PSRR (2.2 < Vdd < 3.0) PSRR (2.0 < Vdd < 2.2) PSRR (Vdd < 2.0) 24 30 12 0 For any resolution Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution. 1 1/(500fF* Data-Clock) 1/(400fF* Data-Clock) dB dB dB dB 5 1/(300fF* Data-Clock) %FSR
Egain RIN
Gain Error Input Resistance
Note 5. Monotonicity is not guaranteed.
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DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VPPOR3 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b, HPOR = 0 PORLEV[1:0] = 00b, HPOR = 1 PORLEV[1:0] = 01b, HPOR = 1 PORLEV[1:0] = 10b, HPOR = 1 Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Conditions Vdd must be greater than or equal to 1.71V during startup, reset from the XRES pin, or reset from watchdog. Min 1.61 - Typ 1.66 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 1.90 1.80 4.73 Max 1.71 2.41 2.66 2.95 2.51 2.78 2.99 3.09 3.20 2.32 1.84 4.83 Units V V V V V V V V V V V V
2.40[6] 2.64[7] 2.85[8] 2.95 3.06 1.84 1.75[9] 4.62
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 24. DC Programming Specifications Symbol Description Conditions Min 1.71 - See the appropriate DC General Purpose IO Specifications on page 19 See appropriate DC General Purpose IO Specifications on page 19 table on pages 15 or 16 - VIH Typ - 5 - - Max 5.25 25 VIL - Units V mA V V VddIWRITE Supply Voltage for Flash Write Operations IDDP VILP VIHP Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify
IILP
Input Current when Applying Vilp Driving internal pull down resistor to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp Driving internal pull down resistor to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify See appropriate DC General Purpose IO Specifications on page 19 table on page 16. For Vdd > 3V use VOH4 in Table 13 on page 18. Erase/write cycles per block Following maximum Flash write cycles; ambient temperature of 55C
-
-
0.2
mA
IIHP
-
-
1.5
mA
VOLP VOHP
- VOH
- -
Vss + 0.75 Vdd
V V
FlashENPB Flash Write Endurance FlashDR Flash Data Retention
50,000 10
- 20
- -
Years
Notes 6. Always greater than 50 mV above VPPOR1 voltage for falling supply. 7. Always greater than 50 mV above VPPOR2 voltage for falling supply. 8. Always greater than 50 mV above VPPOR3 voltage for falling supply. 9. Always greater than 50 mV above VPPOR0 voltage for falling supply.
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AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 25. AC Chip-Level Specifications Symbol FCPU F32K1 FIMO24 FIMO12 FIMO6 DCIMO TRAMP TXRST TXRST2 Description CPU Frequency Internal Low Speed Oscillator Frequency Internal Main Oscillator Frequency at 24 MHz Setting Internal Main Oscillator Frequency at 12 MHz Setting Internal Main Oscillator Frequency at 6 MHz Setting Duty Cycle of IMO Supply Ramp Time External Reset Pulse Width at Power Up After supply voltage is valid External Reset Pulse Width after Power Applies after part has booted Up[10] Conditions Min 5.7 19 22.8 11.4 5.7 40 20 1 10 Typ - 32 24 12 6.0 50 - Max 25.2 50 25.2 12.6 6.3 60 - Units MHz kHz MHz MHz MHz % s ms s
Note 10. The minimum required XRES pulse length is longer when programming the device (see Table 32 on page 28).
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AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. AC GPIO Specifications Symbol FGPIO Description GPIO Operating Frequency Conditions Normal Strong Mode Port 0, 1 Min 0 0 TRise23 TRise23L TRise01 TRise01L TFall TFallL Rise Time, Strong Mode, Cload = 50 pF Ports 2 or 3 Rise Time, Strong Mode Low Supply, Cload = 50 pF, Ports 2 or 3 Rise Time, Strong Mode, Cload = 50 pF Ports 0 or 1 Rise Time, Strong Mode Low Supply, Cload = 50 pF, Ports 0 or 1 Fall Time, Strong Mode, Cload = 50 pF All Ports Fall Time, Strong Mode Low Supply, Cload = 50 pF, All Ports Vdd = 3.0 to 3.6V, 10% - 90% Vdd = 1.71 to 3.0V, 10% - 90% Vdd = 3.0 to 3.6V, 10% - 90% LDO enabled or disabled Vdd = 1.71 to 3.0V, 10% - 90% LDO enabled or disabled Vdd = 3.0 to 3.6V, 10% - 90% Vdd = 1.71 to 3.0V, 10% - 90% 15 15 10 10 10 10 Typ - - - - - - - - Max Units 6 MHz for MHz 1.71Vns ns ns ns ns ns
Figure 12. GPIO Timing Diagram
90% GPIO Pin Output Voltage 10%
TRise23 TRise01 TRise23L TRise01L
TFall TFallL
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Table 27.AC Characteristics - USB Data Timings Symbol Tdrate Tdjr1 Tdjr2 Tudj1 Tudj2 Tfdeop Tfeopt Tfeopr Tfst Description Full speed data rate Receiver data jitter tolerance Receiver data jitter tolerance Driver differential jitter Driver differential jitter Source jitter for differential transition Source SE0 interval of EOP Receiver SE0 interval of EOP Width of SE0 interval during differential transition Conditions Average bit rate To next transition To pair transition To next transition To pair transition To SE0 transition Min 12-0.25% -18.5 -9 -3.5 -4.0 -2 160 82 Typ 12 - - - - - - - - 14 Max 12 + 0.25% 18.5 9 3.5 4.0 5 175 Units MHz ns ns ns ns ns ns ns ns
Table 28.AC Characteristics - USB Driver Symbol Tr Tf TR Vcrs Description Transition rise time Transition fall time Rise/fall time matching Output signal crossover voltage 50 pF 50 pF Conditions Min 4 4 90.00 1.3 Typ - - - - Max 20 20 111.1 2.0 Units ns ns % V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 29. AC Low Power Comparator Specifications Symbol TLPC Description Conditions Min Typ Max 100 Units ns Comparator Response Time, 50 50 mV overdrive does not include mV Overdrive offset voltage.
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 30. AC Analog Mux Bus Specifications Symbol FSW Description Switch Rate Conditions Maximum pin voltage when measuring switch rate is 1.8Vp-p Min - Typ - Max 6.3 Units MHz
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 31. AC External Clock Specifications Symbol FOSCEXT Frequency - - - High Period Low Period Power Up IMO to Switch Description Conditions Min 0.750 20.6 20.6 150 Typ - - - - Max 25.2 5300 - - Units MHz ns ns s
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AC Programming Specifications
Figure 13. AC Waveform
SCLK (P1[1])
T RSCLK
T FSCLK
SDATA (P1[0])
TSSCLK
T HSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 32. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 TXRST3 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK External Reset Pulse Width after Power Up Conditions Min 1 1 40 40 0 - - - - - 263 Typ - - - - - - - - - - - Max 20 20 - - 8 18 25 60 85 130 - Units ns ns ns ns MHz ms ms ns ns ns s
3.6 < Vdd 3.0 Vdd 3.6 1.71 Vdd 3.0 Required to enter programming mode when coming out of sleep
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 33. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - - - - - - Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[11] 0.6 1.3 0 Max 400 - - - - - - - - 50 Units kHz s s s s s ns s s ns
FSCLI2C SCL Clock Frequency THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock HIGH Period of the SCL Clock THIGHI2C TSUSTAI2C Setup Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time for STOP Condition TBUFI2C Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. TSPI2C
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
Note 11. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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Table 34. SPI Master AC Specifications Symbol FSCLK Description SCLK clock frequency Conditions VDD 2.4V VDD < 2.4V 50 VDD 2.4V VDD < 2.4V 60 100 40 40 40 Min Typ Max 6 3 Units MHz
DC TSETUP THOLD TOUT_VAL TOUT_HIGH
SCLK duty cycle MISO to SCLK setup time SCLK to MISO hold time SCLK to MOSI valid time MOSI high time
% ns ns ns ns
Table 35. SPI Slave AC Specifications Symbol FSCLK Description SCLK clock frequency Conditions VDD 2.4V VDD < 2.4V 41.67 41.67 30 50 153 125 50 2/SCLK 2/SCLK Min Typ Max 12 6 Units MHz
TLOW THIGH TSETUP THOLD TSS_MISO TSCLK_MISO TSS_HIGH TSS_CLK TCLK_SS
SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high
ns ns ns ns ns ns ns ns ns
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Packaging Information
This section illustrates the packaging specifications for the CY8C20X36A/46A/66A/96A PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 15. 16-pin QFN No E-pad 3x3mm Package Outline (Sawn)
001-09116 *D
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Figure 16. 24-Pin (4x4 x 0.6 mm) QFN
001-13937 *B
Figure 17. 32-Pin (5x5 x 0.6 mm) QFN
001-42168 *C
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Figure 18. 48-Pin (300 MIL) SSOP
.020
24 1
0.395 0.420 0.292 0.299
DIMENSIONS IN INCHES MIN.
MAX.
25
48
0.620 0.630
0.088 0.092
0.095 0.110
SEATING PLANE GAUGE PLANE
.010
0.005 0.010
0.025 BSC
0.004
0.008 0.0135 0.008 0.016 0-8
0.024 0.040
51-85061 *C
Figure 19. 48-Pin (7x7 mm) QFN
001-13191 *C
Important Notes

For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the low power PSoC device.
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Thermal Impedances
Table 36. Thermal Impedances per Package Package 16 QFN 24 QFN[13] 32 QFN[13] 48 SSOP 48 QFN[13] Typical JA [12] 32.69oC/W 20.90oC/W 19.51oC/W 69oC/W 17.68oC/W
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability. Table 37. Solder Reflow Peak Temperature Package 16 QFN 24 QFN 32 QFN 48 SSOP 48 QFN Minimum Peak Temperature[14] 240oC 240oC 240oC 220oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC
Notes 12. TJ = TA + Power x JA. 13. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. 14. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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Development Tool Selection
Software
PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. PSoC Programmer PSoC Programmer is flexible enough and is used on the bench in development and is also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of cost at http://www.cypress.com/psocprogrammer.
Evaluation Tools
All evaluation tools are sold at the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:

MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443A-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Development Kits
All development kits are sold at the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes:

CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:

Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466A-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66A Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466A-24PXI 28-PDIP Chip Samples
CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794A-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:

PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack
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Device Programmers
All device programmers are purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:

CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:

CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
Modular Programmer Base Three Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
Accessories (Emulation and Programming)
Table 38. Emulation and Programming Accessories Part Number CY8C20236A-24LKXI CY8C20246A-24LKXI CY8C20336A-24LQXI CY8C20346A-24LQXI CY8C20396A-24LQXI CY8C20436A-24LQXI CY8C20446A-24LQXI CY8C20466A-24LQXI CY8C20496A-24LQXI CY8C20536A-24PVXI CY8C20546A-24PVXI CY8C20566A-24PVXI CY8C20636A-24LTXI CY8C20646A-24LTXI CY8C20666A-24LTXI Pin Package 16 QFN 16 QFN 24 QFN 24 QFN 24 QFN 32 QFN 32 QFN 32 QFN 32 QFN 48 SSOP 48 SSOP 48 SSOP 48 QFN 48 QFN 48 QFN CY3250-20X66 CY3250-20X66 CY3250-20X66 CY3250-20666QFN CY3250-20666QFN CY3250-20666QFN CY3250-20466QFN CY3250-20466QFN CY3250-20466QFN Flex-Pod Kit[15] CY3250-20266QFN CY3250-20266QFN CY3250-20366QFN CY3250-20366QFN Foot Kit[16] CY3250-16QFN-RK CY3250-16QFN-FK CY3250-24QFN-FK CY3250-24QFN-FK Not Available CY3250-32QFN-RK CY3250-32QFN-FK CY3250-32QFN-FK Not Available CY3250-48SSOP-FK CY3250-48SSOP-FK CY3250-48SSOP-FK CY3250-48QFN-FK CY3250-48QFN-FK CY3250-48QFN-FK See note 17 See note 17 See note 17 See note 17 See note 17 See note 17 See note 15 See note 17 See note 17 Adapter[17] See note 15 See note 17 See note 15 See note 17
Third-Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/?rID2748.
Notes 15. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 16. Foot kit includes surface mount feet that can be soldered to the target PCB. 17. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
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Ordering Information
The following table lists the CY8C20X36A/46A/66A/96A PSoC devices' key package features and ordering codes. Table 39. PSoC Device Key Features and Ordering Information
Package
16-Pin (3x3x0.6mm) QFN 16-Pin (3x3x0.6mm) QFN (Tape and Reel) 16 Pin (3x3 x 0.6 mm) QFN 16 Pin (3x3 x 0.6 mm) QFN (Tape and Reel) 24-Pin (4x4x0.6mm) QFN 24-Pin (4x4x0.6mm) QFN (Tape and Reel) 24 Pin (4x4 x 0.6 mm) QFN 24 Pin (4x4 x 0.6 mm) QFN (Tape and Reel) 24-Pin (4x4x0.6mm) QFN 24-Pin (4x4x0.6mm) QFN (Tape and Reel) 32-Pin (5x5x0.6mm) QFN 32-Pin (5x5x0.6mm) QFN (Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN 32 Pin (5x5 x 0.6 mm) QFN (Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN 32 Pin (5x5 x 0.6 mm) QFN (Tape and Reel) 32 Pin (5x5 x 0.6 mm) QFN 32 Pin (5x5 x 0.6 mm) QFN (Tape and Reel) 48-Pin SSOP 48-Pin SSOP (Tape and Reel) 48-Pin SSOP 48-Pin SSOP (Tape and Reel) 48-Pin SSOP 48-Pin SSOP (Tape and Reel) 48 Pin (7x7 mm) QFN 48 Pin (7x7 mm) QFN (Tape and Reel) 48 Pin (7x7 mm) QFN 48 Pin (7x7 mm) QFN (Tape and Reel) 48 Pin (7x7 mm) QFN 48 Pin (7x7 mm) QFN (Tape and Reel) 48 Pin (7x7 mm) QFN (OCD)[4]
Ordering Code
CY8C20236A-24LKXI CY8C20236A-24LKXIT CY8C20246A-24LKXI CY8C20246A-24LKXIT CY8C20336A-24LQXI CY8C20336A-24LQXIT CY8C20346A-24LQXI CY8C20346A-24LQXIT CY8C20396A-24LQXI CY8C20396A-24LQXIT CY8C20436A-24LQXI CY8C20436A-24LQXIT CY8C20446A-24LQXI CY8C20446A-24LQXIT CY8C20466A-24LQXI CY8C20466A-24LQXIT CY8C20496A-24LQXI CY8C20496A-24LQXIT CY8C20536A-24PVXI CY8C20536A-24PVXIT CY8C20546A-24PVXI CY8C20546A-24PVXIT CY8C20566A-24PVXI CY8C20566A-24PVXIT CY8C20636A-24LTXI CY8C20636A-24LTXIT CY8C20646A-24LTXI CY8C20646A-24LTXIT CY8C20666A-24LTXI CY8C20666A-24LTXIT CY8C20066A-24LTXI
Flash (Bytes)
8K 8K 16K 16K 8K 8K 16K 16K 16K 16K 8K 8K 16K 16K 32K 32K 16K 16K 8K 8K 16K 16K 32K 32K 8K 8K 16K 16K 32K 32K 32K
SRAM (Bytes)
1K 1K 2K 2K 1K 1K 2K 2K 2K 2K 1K 1K 2K 2K 2K 2K 2K 2K 1K 1K 2K 2K 2K 2K 1K 1K 2K 2K 2K 2K 2K
CapSense Blocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Digital I/O Pins
13 13 13 13 20 20 20 20 19 19 28 28 28 28 28 28 25 25 36 36 36 36 36 36 36 36 36 36 36 36 36
Analog Inputs[18]
13 13 13 13 20 20 20 20 19 19 28 28 28 28 28 28 25 25 36 36 36 36 36 36 36 36 36 36 36 36 36
XRES Pin
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
USB
No No No No No No No No Yes Yes No No No No No No No No No No No No No No No No Yes Yes Yes Yes Yes
Notes 18. Dual-function Digital I/O Pins also connect to the common analog mux.
Document Number: 001-54459 Rev. **
Page 37 of 38
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CY8C20X36A/46A/66A/96A
Document History Page
Document Title: CY8C20X36A/46A/66A/96A CapSense(R) Applications Document Number: 001-54459 Revision ** ECN 2737924 Origin of Change SNV Submission Date 07/14/09 Description of Change New silicon and document (Revision **).
Sales, Solutions, and Legal Information
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54459 Rev. **
Revised July 14, 2009
Page 38 of 38
PSoC DesignerTM is a trademark and PSoC(R) and CapSense(R) are registered trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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